2026-05-29 — views $SIFV · SiFive · Performance P570 Gen 3 (64-bit RISC-V IP core)

SiFive P570 Gen 3 — RISC-V core for AI and edge applications

SiFive unveiled the Performance P570 Gen 3, a 64-bit RVA23-compliant RISC-V processor targeting edge AI, consumer, and IoT markets. The core delivers 7–13% SpecInt improvements and up to 21X gains on AI workloads versus its predecessor, while reducing dynamic power by 13%.

For two decades, Arm has owned consumer silicon, from mobile phones to IoT gateways to automotive SoCs. That dominance rested on one bet: proprietary instruction sets are faster, simpler, and better funded than open alternatives.

SiFive’s May 2026 announcement of the Performance P570 Gen 3 tests that thesis. The core is a 3-wide, 13-stage out-of-order RISC-V processor with a 128-bit vector pipeline, scaling to 16 cores per complex. On SpecInt 2006/2017 benchmarks it delivers 7–13% improvements over its P550 Gen1 predecessor. On AI workloads, the gains reach 21X. Dynamic power drops 13%. All while holding to the RVA23 ISA profile that unifies RISC-V’s fragmented instruction-set landscape.

The architecture underneath

The P570 Gen 3 is not a tick-tock refresh. Its three-wide issue pipeline, 13 execution stages, and 128-bit vector engine signal an architecture engineered for consumer and edge AI workloads — the exact segment where Arm’s Cortex-X and Neoverse lines compete. Out-of-order execution, branch prediction, and cache hierarchy are all commodity in 2026; what matters is whether the ISA itself becomes commodity.

SiFive pairs the core with companion system IP: an advanced interrupt architecture (AIA), a second-generation IOMMU, and WorldGuard security primitives. Together, these target the full stack needed for edge AI accelerators, consumer appliances, and commercial IoT gateways.

Context: $400M in RISC-V conviction

The P570 Gen 3 announcement lands just weeks after SiFive closed a $400 million Series G funding round in April 2026. That capital is explicitly earmarked for high-performance, data-center-grade RISC-V IP — signaling that venture capital and SiFive’s customers (hyperscalers, chip OEMs) now view RISC-V maturity as credible enough to bet nine figures on.

For context, Arm’s IP licensing revenues exceed $600M annually, but nearly all of that comes from Cortex-A (high-end mobile/server) and Cortex-M (IoT microcontrollers). The consumer AI edge — think TensorFlow lite on edge cameras, on-device LLM inference, automotive neural accelerators — remains Arm-dominated by default, not by technical necessity. SiFive is building the IP to change that.

Practitioner note

If you are an SoC architect evaluating P570 Gen 3 for a consumer or edge-AI design:

RVA23 compliance is the unlock: it guarantees a stable ISA baseline. Prior RISC-V generations fragmented across vendor-specific extensions; RVA23 commoditizes the baseline, reducing your software porting cost.
21X AI gains over P550 Gen1 are measured on specific workloads (vector and FMA-heavy ops). Run your own benchmarks on representative edge-AI models (MobileNet, BERT quantized, Yolo) before committing.
Time to tapeout: licensing P570 Gen 3 requires Cadence/Synopsys flow integration; plan 12–18 months to first silicon if integrating new compute, longer if adding security or custom memory controllers.
Ecosystem: RISC-V compiler maturity (GCC, LLVM) is now production-grade. Tool fragmentation (ModelSim vs Xsim, Questa licensing) mirrors Arm’s; vendor lock-in still exists, just under different names.

The closing angle

RISC-V’s credibility inflection is now undeniable. Mattel uses SiFive IP in consumer toys. Espressif ships billions of RISC-V units in IoT gateways. Western Digital built a subsidiary (SiFive itself, partially) around the architecture. And now, with a $400M war chest and a 64-bit, out-of-order core competitive with Cortex-A78, SiFive is testing whether open instruction sets can finally break Arm’s stranglehold on consumer silicon.

The P570 Gen 3 will not dethrone Arm overnight. But it signals the moment when choosing RISC-V becomes a valid engineering decision, not a startup purity play. That moment is 2026.