2026-05-15 — views $LRCX · Lam Research · Etch · Deposition · Clean · WFE — etch + 3D scaling
Lam Research (LRCX) — high-aspect-ratio etch leadership, directly leveraged to HBM
LRCX owns high-aspect-ratio (HAR) etch — the chamber tools that carve deep, narrow holes through 200+ layers of 3D NAND and DRAM stacks. The cleanest WFE leveraged play on HBM volume growth.
Lam Research (NASDAQ: LRCX) is the second-largest WFE company by revenue and the etch specialist. Where Applied Materials owns breadth across deposition, etch, CMP, and implant, Lam goes deep on a narrower set — etch above all, with deposition (ALD, PECVD) and wafer clean as the second and third legs. The narrower focus means Lam is more directly leveraged to specific structural trends: HBM, 3D NAND scaling, gate-all-around (GAA) transistors. For builders, Lam is the cleanest pure read on memory cycle + 3D scaling.
Three product lines, etch is the crown jewel
| Segment | What it does | Lam flagship |
|---|---|---|
| Etch | Carves features into the wafer — conductor etch, dielectric etch, deep silicon etch | Kiyo (conductor), Flex (dielectric), Sense.i (advanced-node) |
| Deposition | Lays down thin films — ALD W, PECVD, electroplate | ALTUS (ALD tungsten), VECTOR (PECVD), SABRE (electroplate) |
| Clean | Removes residues and contaminants between process steps | Coronus, Da Vinci |
Etch is roughly half of Lam’s revenue and the source of its competitive moat. At advanced nodes, etch is harder than it sounds — chambers must carve features only nanometers wide while controlling sidewall angle, depth uniformity, and selectivity. Lam has shipped 100,000+ etch chambers cumulatively; that installed base creates compounding advantages in recipe development.
High-aspect-ratio etch — the HBM moat
The 2024-2026 boom in High Bandwidth Memory (HBM) is fundamentally a 3D NAND / 3D DRAM stacking story. HBM stacks 8, 12, or 16 DRAM dies vertically, connected by through-silicon vias (TSVs). The TSVs themselves require Lam’s HAR etch capability — drilling deep, narrow vertical holes through 100+ micrometers of silicon.
Beyond HBM specifically, 3D NAND scaling depends on the same HAR etch capability. Modern NAND is 200+ layers deep; each layer requires precise vertical etching. Lam’s competitive position here is sometimes overstated as a “monopoly” — Tokyo Electron is a credible competitor at advanced nodes — but Lam ships the deepest HAR etch chambers in production volume today, and its installed base in HBM and 3D NAND lines is substantial.
For builders thinking about AI memory: every HBM3, HBM3E, and HBM4 module shipped to NVDA, AMD, or any hyperscale buyer required Lam HAR etch chambers in the supply chain. The path from “AI training compute grows” to “Lam orders grow” is shorter and more direct than for any other WFE name.
Gate-all-around (GAA) — the logic node bet
The second growth vector is the transition from FinFET to GAA transistors at 2nm and below. GAA introduces new etch challenges: precise removal of sacrificial layers, atomic-scale selectivity, and ultra-clean post-etch surfaces. Lam has been positioning for this transition for several years — Sense.i is the flagship advanced-node etch tool. If TSMC’s 2nm (N2) and Samsung’s 2nm GAA ramps go as planned, Lam captures incremental etch dollars per wafer relative to FinFET.
Why this matters for builders
The case for Lam comes in three layers:
- Memory cycle exposure. HBM is structurally growing for AI; conventional DRAM and NAND are cyclical. Lam’s revenue mix means memory cycles hit harder than for AMAT, both up and down.
- 3D scaling is non-optional. Whether memory or logic, the industry is going vertical. HAR etch capacity is a binding constraint, and Lam is one of the few suppliers with the chamber technology.
- Concentration is the cost. Lam’s narrower focus is leverage in good times and exposure in bad. Memory downcycles hit Lam harder than they hit AMAT.
Practitioner note
For builders evaluating exposure:
- The leading indicator is HBM capacity announcements. SK Hynix, Samsung, and Micron HBM capacity expansion plans flow directly into Lam etch orders 1-2 quarters later. Read the memory-maker earnings calls for capex guidance, not just Lam’s.
- Service mix matters less here than at AMAT. Lam’s service business exists but is a smaller share of revenue. Systems revenue swings dominate.
- GAA timing is the watch list item. TSMC N2 production ramp (currently planned for late 2025 / early 2026 at volume) is the trigger that converts GAA from R&D opportunity to revenue. Same for Samsung 2nm. Slippage at either pushes Lam’s GAA upside out.
- China exposure is meaningful. Lam’s pre-control-tightening China revenue share was higher than AMAT’s. Export-control evolution remains the largest single regulatory risk to the model.
The under-considered angle: clean is the quiet growth segment. Coronus and Da Vinci wafer-clean tools are required between every other process step, and the number of process steps grows with node complexity. As nodes get more complex, clean tool count per wafer grows. It’s not glamorous and gets little airtime, but it’s a structural compounder.