2026-06-16 👁️ — views · TSMC (NYSE: TSM) · CoPoS panel-packaging line, Longtan facility · Panel-level advanced packaging — CoPoS (Chip-on-Panel-on-Substrate)

TSMC runs a dual-track vendor race on its CoPoS panel-packaging pilot line at Longtan — global majors vs. Taiwanese suppliers, head-to-head

TSMC's Longtan CoPoS pilot pits global equipment vendors against Taiwanese suppliers on process stability, cost, and lead time. The 310×310 mm panel format targets AI reticle-size limits; mass production targets 2028–29.

What TSMC is doing at Longtan

According to a June 16 TrendForce report, TSMC’s Longtan facility — the site of its advanced packaging R&D and pilot lines — is operating two parallel equipment evaluation tracks on its CoPoS (Chip-on-Panel-on-Substrate) pilot line. One track uses tools from global semiconductor-equipment majors (understood to include Applied Materials, TEL, and Lam Research); the second track uses tools from Taiwanese suppliers. The two tracks are evaluated head-to-head on process stability, equipment cost, and lead time.

The process being piloted is panel-level packaging on 310×310 mm glass substrates — significantly larger than the 300 mm wafers CoWoS currently uses. CoPoS is TSMC’s term for embedding chips (including compute dies and memory) into a glass panel, then routing interconnects at wafer-fab-level precision across the larger surface area.

Why panel-level packaging matters for AI

The driver is geometry. NVIDIA’s Hopper and Blackwell chips are already pushing CoWoS-L packages to their maximum reticle size — roughly 900 mm² of interconnect substrate. The next GPU generation (Rubin, Vera Rubin) will need to connect even more dies across even larger surfaces. A 300 mm round wafer limits the maximum substrate area available per “panel” of packages; a 310×310 mm square glass panel is nearly 40% larger in area per unit, enabling larger single packages and better die-per-panel economics.

The implications for AI infrastructure are direct: if TSMC can deliver CoPoS at volume, the per-chip limitation on GPU-to-HBM bandwidth imposed by CoWoS substrate size largely disappears. Rubin-class and future chips could host more HBM4 stacks per package, more NVLink dies, and tighter chiplet pitch — all within a single CoPoS package rather than a multi-package system.

The dual-track strategy

Running two vendor tracks in parallel is unusual and expensive. TSMC is doing it for several reasons:

Supply resilience. TSMC’s CoWoS ramp in 2023–2024 was supply-chain-constrained — one of the bottlenecks was ABF substrate availability, but another was tooling and materials sourcing concentrated in a small number of suppliers. Panel-level packaging uses glass substrates (different supply chain) and a different equipment set. Starting with parallel tracks buys optionality on who can deliver.

Cost pressure. Glass panel packaging processes require large-format deposition, lithography, and etch tools that are technically similar to but not identical with wafer-format equivalents. Taiwanese suppliers can potentially offer lower cost and shorter lead times for custom configurations, but global majors have more mature process libraries. Running both tracks gives TSMC real cost and yield data rather than vendor-quoted estimates.

Geopolitical hedging. TSMC has been under sustained pressure from the Taiwan government and its customers to reduce single-source dependencies. A pilot where a Taiwanese supply chain can demonstrate parity with global majors is politically useful regardless of which track wins.

Timeline and mass production

The CoPoS pilot at Longtan is targeting mass production readiness for 2028–2029. That timeline aligns with the likely production ramp for whatever follows Vera Rubin (the next-next NVIDIA GPU generation) and with AMD’s post-MI400 roadmap. The 2026 pilot is a roughly 24–36 month lead for production qualification — tight for a process as novel as panel-level packaging at AI-chip precision.

The dual-track decision needs to resolve to a single production track, or a tiered production/backup arrangement, before TSMC can commit to customer product designs that depend on CoPoS. That decision window is likely 2027 based on the 2028 mass production target.

What to watch in the equipment race

The global majors’ advantage is depth of knowledge; Taiwanese suppliers’ advantage is proximity and responsiveness. TSMC’s ideal outcome is probably a hybrid: global-major tools for the most process-critical steps (fine-pitch lithography, deposition uniformity) and Taiwanese tools for peripheral steps where cost and lead time matter more than marginal performance.

Practitioner note

For investors following the AI-packaging supply chain, the CoPoS dual-track announcement has two implications. Near-term: it confirms TSMC is in serious R&D spending mode on panel packaging — this is not a roadmap slide, it is a running pilot line with competing vendor hardware. Longer-term: the track that wins this evaluation becomes the primary tooling supplier for what may be the largest advanced-packaging build-out of the decade. Applied Materials, TEL, and Lam all have meaningful revenue exposure to packaging; the Taiwanese competitors are mostly public on the TWSE and less followed by Western analysts.

For anyone building AI infrastructure models with a 3–5 year horizon, CoPoS is the technology that removes the current ceiling on per-package GPU die count. The packaging substrate is the binding constraint on Rubin-class chips and everything that follows. This pilot is where that constraint either lifts or doesn’t.

Under-considered angle

The physics of panel-level packaging creates a problem that doesn’t exist at wafer level: panel bow and warpage. Glass panels at 310×310 mm and sub-millimeter thickness flex under thermal cycling in ways that 300 mm silicon wafers do not. Getting copper pillar bonding, thin-film RDL routing, and chip attachment to all work reliably across a warped glass panel is a materials-science problem as much as an equipment problem. The vendor that solves bow compensation — either through materials process control or through adaptive lithography that adjusts for panel shape — wins the pilot regardless of cost or lead time. That is the under-reported technical variable driving the dual-track evaluation: TSMC is not just evaluating tools, it is evaluating whose process control can handle glass.

Sources

• TSMC Reportedly Runs Dual-Track Evaluation on CoPoS Pilot Line, Sparking Global vs. Local Vendor Competition — TrendForce ↗
• TSMC CoPoS panel-level packaging — Digitimes coverage ↗