2026-05-19 — views $RMBS · Rambus + Synopsys · HBM3E / HBM4 controller + PHY IP
HBM controller race — Rambus vs Synopsys for AI accelerator memory IP
The HBM controller IP race between Rambus (RMBS) and Synopsys (SNPS) decides which AI accelerator silicon ships on time. Every NVIDIA / AMD / hyperscaler ASIC carries 4-8 HBM stacks; each stack uses controller + PHY IP licensed from one of these two.
Every NVIDIA Blackwell, every AMD MI400, every hyperscaler AI accelerator carries 4 to 8 HBM stacks sitting next to the compute die. Each stack talks to the SoC through a controller + PHY (physical layer) IP block licensed from one of two vendors: Rambus (RMBS) or Synopsys (SNPS).
This is the most under-discussed bottleneck in AI infrastructure. CoWoS got the headlines in 2024-2025; HBM controllers will get them in 2026-2027.
What an HBM controller IP block actually does
HBM (High Bandwidth Memory) is a 3D-stacked DRAM that lives next to the compute die on a silicon interposer. To talk to it, the SoC needs:
| Block | What it does |
|---|---|
| Memory controller (digital) | Translates SoC memory requests into HBM commands (read/write/refresh/training) |
| PHY (physical layer) | The analog/mixed-signal layer that actually drives the >1000-pin HBM interface at 6.4 Gbps+ per pin |
| Refresh + ECC + RAS logic | Reliability, availability, serviceability — keeps HBM stable under sustained AI workloads |
| Power management | HBM4 supports DVFS (dynamic voltage/frequency scaling); controller manages it |
The controller + PHY pair is licensed as a unit. Customers (NVIDIA, AMD, hyperscalers, sometimes the HBM vendor’s own reference design) instantiate it next to their compute die.
The two vendors compared
Rambus (RMBS) — memory IP specialist
| Aspect | Rambus position |
|---|---|
| HBM3E controller | Production, multiple customer designs |
| HBM4 controller | Tape-out announced 2025; production silicon 2026 |
| PHY support | 8.4-9.6 Gbps/pin (HBM4 spec); also DDR5 / LPDDR5X / GDDR7 |
| Reliability features | On-die ECC, post-package repair (PPR), RAS counters |
| Customers (disclosed) | NVIDIA (via HBM vendor reference), AMD, multiple hyperscaler ASIC designs |
| Business model | Pure IP license + per-stack royalty |
| Strengths | 30+ years of memory IP heritage; tightest with SK Hynix, Micron, Samsung reference flows |
| Weaknesses | Smaller company (~$1B cap); less able to bundle with broader EDA license |
Synopsys (SNPS) — broader IP catalog including HBM
| Aspect | Synopsys position |
|---|---|
| HBM3E controller | Production via DesignWare; bundled in chiplet reference flows |
| HBM4 controller | Announced 2024; sampling 2025; production tape-outs late 2025 |
| PHY support | Matches HBM4 spec (8.4 Gbps/pin baseline, 9.6+ in roadmap) |
| Reliability features | ECC, RAS, integrated with DesignWare verification IP |
| Customers (disclosed) | Hyperscaler ASIC designs (Google TPU, AWS Trainium, MS Maia all use Synopsys IP somewhere in the design), Intel, AMD MI300/400 cycle |
| Business model | IP license, often bundled with EDA tool deal |
| Strengths | Single-vendor convenience (EDA + IP + verification + ANSYS simulation now); deepest TSMC reference flow integration |
| Weaknesses | Memory IP is one of many product lines; less specialized than Rambus |
Why the race matters for AI capacity
Three structural reasons HBM controllers are about to become the constraint:
1. HBM4 is mandatory on next-gen AI accelerators
The Blackwell-class successors (NVIDIA Rubin, AMD MI500-class, Intel Falcon Shores 2, hyperscaler ASIC v2) all target HBM4 at 12-Hi stacks delivering ~2 TB/s per stack at 36-48 GB capacity. HBM3E is end-of-life for new flagship AI silicon by mid-2026.
A new HBM4 controller IP block must be:
- Validated on the target foundry (TSMC N3/N2)
- Co-designed with the HBM vendor’s stack
- Tape-out + first silicon in the customer’s compute die
This is a 12-18 month timeline from IP availability to shipping silicon. If Rambus’s or Synopsys’s HBM4 IP slips, downstream customers slip too.
2. Volume mathematics — every stack pays royalty
Approximate 2026 unit math:
- 5 million Blackwell-class GPUs ship in 2026 (per current analyst consensus)
- × 8 HBM stacks per GPU = 40 million HBM stacks
- × $1-5 controller IP royalty per stack = $40-200M annualized just from controller IP — on top of memory revenue
Now add AMD MI400 + hyperscaler ASICs. The total HBM controller IP market in 2026 is plausibly $150-400M, captured almost entirely by Rambus + Synopsys.
3. HBM5 is on the horizon (2027-2028)
JEDEC’s HBM5 working group is targeting 3+ TB/s per stack at 64 GB capacity. The IP layer has to evolve before the silicon ramps. Whichever vendor lands first commercial HBM5 controller wins the next 3-year cycle by default — switching cost on HBM IP is high once a design wins.
Who’s using which
Disclosure is thin (HBM customer relationships are NDA-heavy), but the publicly-traceable wins:
| Silicon | HBM gen | Likely controller IP | Notes |
|---|---|---|---|
| NVIDIA Blackwell B200 | HBM3E | Mixed (Rambus + Synopsys roles) | Multiple HBM vendors → multiple IP touchpoints |
| AMD MI300X / MI325X | HBM3 | Rambus reference flow | Long-standing AMD-Rambus relationship |
| AMD MI400 (upcoming) | HBM4 | Likely Synopsys-heavy | Synopsys DesignWare HBM4 announced co-design |
| Google TPU v6/v7 | HBM3E | Synopsys (in-house customization) | Disclosed in 2024 TPU presentation |
| AWS Trainium 3 | HBM3E | Synopsys | Per AWS silicon design partner disclosures |
| Intel Falcon Shores 2 | HBM3E → HBM4 | Synopsys + Intel internal | Mixed model |
| Microsoft Maia 2 | HBM3E | Likely Synopsys | Hyperscaler ASIC patterns favor Synopsys bundling |
Headline observation: Hyperscalers tend to go Synopsys (bundled with their EDA spend). Pure-merchant accelerator vendors (NVIDIA, AMD) tend to multi-source. Rambus is gaining share in HBM4 cycle because of dedicated HBM-vendor co-design, but Synopsys remains larger in absolute revenue.
Risks to both vendors
- HBM vendor in-housing. SK Hynix has its own controller IP team; if they start offering pre-validated controllers as part of HBM SKU, both Rambus and Synopsys lose royalty per stack on those designs.
- Customer in-housing. Hyperscalers with deep silicon teams (Google, AWS) could in-house HBM controllers if they want to fully own the design. Probably 2027-2028 timeline. Caps the addressable market.
- HBM4 spec slippage. The 9.6 Gbps/pin variant is still finalizing in JEDEC. If the spec changes meaningfully, both vendors retape — costly for both.
Practitioner note
For builders / silicon designers:
- If you’re spec’ing a custom AI accelerator, budget 4-6 quarters from IP license signing to first silicon. HBM4 IP availability is the path-of-critical lead time, not compute IP.
- Multi-source HBM controller IP if you can. Both vendors’ silicon is functional; bringing in a backup mid-cycle is hard but having dual sources from the start prevents single-vendor delays from gating tape-out.
- For investors: the HBM controller royalty stream is the most levered to AI server volume + HBM intensity. RMBS is the pure play; SNPS is the bundled play. Both compound through the 2026-2028 HBM4-HBM5 transition.
The under-considered angle: HBM controller IP is the silent compounding layer in AI infrastructure. When industry headlines focus on TSMC capacity, NVIDIA GPU shipments, or memory module ASPs, the per-stack controller royalty just keeps growing — because every accelerator built ships 4-8 stacks. If 2026 sees 50M HBM stacks shipped (across all AI silicon) and that scales to 200M by 2028, the IP layer compounds at silicon-volume pace. It’s invisible until someone runs the math.