2026-05-18 — views $CDNS · Cadence · Innovus · Genus · Tempus · Tensilica · JedAI
Cadence (CDNS) — EDA + Tensilica IP, the co-leader of the duopoly that designs every AI chip
Cadence is the #2 EDA vendor and co-leader of the design-tool duopoly with Synopsys. Cerebrus AI place-and-route + JedAI platform + Tensilica DSP/AI cores. Every Apple A-series, Qualcomm, and Tesla FSD chip uses Cadence tools.
Cadence (NASDAQ: CDNS) is the #2 EDA vendor and co-leader of the design-tool duopoly with Synopsys. Where Synopsys leads on raw IP catalog size, Cadence leads on AI-driven design tools — Cerebrus AI place-and-route and the JedAI generative AI platform are both ahead of Synopsys’ equivalents on per-customer adoption.
What Cadence sells
| Product line | What it is | Where it ships |
|---|---|---|
| Innovus + Genus | Place-and-route + synthesis | Every advanced-node digital design |
| Tempus + Quantus | Static timing + RC extraction | All flagship SoCs and AI accelerators |
| Spectre + Virtuoso | Analog/mixed-signal design + simulation | Every PHY, every PLL, every analog block |
| Tensilica processor IP | DSP + AI cores | >95% of mobile audio/camera ISPs, automotive ADAS |
| Cerebrus + JedAI | AI-driven design (place-and-route, verification) | NVIDIA, Apple, Samsung have all disclosed adoption |
| Allegro PCB | Hardware design platform | Datacenter + automotive systems |
The Cerebrus + JedAI angle
The structural bet that differentiates Cadence: AI-driven design tools deliver PPA improvements that Synopsys can match but customers feel different about. Cerebrus uses reinforcement learning on the place-and-route problem; JedAI is a generative AI platform for verification + debug.
Adoption is well-documented:
- NVIDIA disclosed Cerebrus in the Hopper + Blackwell design cycles
- Apple uses Cadence tools across A-series and M-series (architectural license on ARM, design tools from Cadence)
- TSMC reference flows include both Cerebrus and DSO.ai as approved AI design assistants
The customer that’s neutral between Synopsys and Cadence buys both; the customer that’s been with Cadence for 20 years stays with Cadence. Lock-in is bilateral.
Tensilica — the silent volume play
The non-obvious Cadence revenue tail is Tensilica processor IP — configurable DSP + AI cores licensed into:
- Mobile audio + camera ISPs — >95% of smartphones run Tensilica DSPs in the audio + image processing pipeline. Apple, Qualcomm, MediaTek all use them. Per-device royalty is small (~$0.10-0.50) but volume is billions of units.
- Automotive ADAS — Tesla FSD, BMW, Mercedes camera processing
- Edge AI accelerators — Tensilica HiFi (audio), Vision (image), and Vision Q8 (AI inference) cores
Tensilica is the under-discussed dual to ARM’s mobile dominance: where ARM licenses the CPU, Cadence-Tensilica licenses the DSP that runs alongside it. Different chip, same per-device royalty model.
Comparing to Synopsys
| Cadence | Synopsys | |
|---|---|---|
| EDA share (advanced node) | ~30-35% | ~35-40% |
| IP catalog | ~1500 titles (focused) | ~4500 titles (broad) |
| AI-driven design tools | Cerebrus + JedAI (lead in adoption) | DSO.ai (lead in TSMC reference flow) |
| Specialty IP | Tensilica DSP/AI (mobile dominance) | ARC cores (general purpose) |
| Multi-physics | Limited (Spectre analog) | ANSYS acquisition (full coverage) |
| Market cap | ~$70B | ~$80B |
Cadence is slightly smaller, more focused. Synopsys is the broader play; Cadence is the narrower play with a tighter AI-tooling story. Both are non-replaceable in the customer stack.
What’s driving 2026 growth
Three threads:
- AI accelerator design starts. Every new ASIC (Trainium 3, TPU v7, Microsoft Maia 2, etc.) is a design event that pays Cadence. Custom silicon proliferation = Cadence revenue.
- Automotive ADAS ramp. Tesla FSD, China automakers (BYD, NIO, Xpeng), European premium brands all designing in-house silicon. Cadence wins these because Tensilica + Innovus are the default for ADAS designs.
- 3D-IC + advanced packaging. Chiplets, CoWoS, hybrid bonding — these are emerging EDA problems. Cadence has been ahead on 3D-IC tooling since 2024.
Risks
- Synopsys ANSYS-driven multi-physics push. If multi-physics modeling becomes mandatory for advanced-node design, Synopsys’ ANSYS acquisition advantages Synopsys. Cadence is responding with partnerships but hasn’t matched the integration.
- Cyclical EDA revenue. Like Synopsys, Cadence is somewhat lumpy across node-migration years. Quarterly bookings matter more than quarterly revenue.
- China exposure. Similar export-control risk as Synopsys, ~8-10% revenue.
Practitioner note
For builders:
- If you’re designing analog IP (PLL, ADC, DAC, RF, anything mixed-signal), Cadence Spectre + Virtuoso is the de-facto standard. Synopsys exists in this space but Cadence is the default flow.
- For automotive / edge AI startups, Tensilica processor IP is the cheapest path to a working DSP/AI block in your SoC. Self-licensable, well-documented, large engineer pool that knows it.
- For investors: Cadence is the higher-multiple, lower-IP-catalog play vs. Synopsys. Both move together with overall semis design volume; Cadence has slightly more leverage to AI accelerator design starts specifically.
The under-considered angle: the EDA duopoly is the only “AI” exposure that’s also fab-cycle agnostic. When TSMC capacity tightens, chip design slows down only marginally (designers iterate longer rather than less); when TSMC capacity loosens, design volume rises. EDA revenue is steadier than chip-revenue across cycles — and Cadence + Synopsys both compound through it.