2026-05-18 — views $SNPS · Synopsys · Design Compiler · ICC · PrimeTime · IP catalog

Synopsys (SNPS) — the EDA + IP duopoly that designs every AI accelerator

Synopsys is the largest EDA vendor and the largest commercial IP catalog (~4500 titles). Every NVIDIA, AMD, hyperscaler ASIC, and ARM-based server CPU is designed in Synopsys tooling. ANSYS $35B acquisition closed 2025.

Synopsys (NASDAQ: SNPS) is the largest EDA vendor and largest commercial IP catalog in the world. Every NVIDIA Blackwell, every AMD MI400, every hyperscaler custom ASIC (Google TPU, AWS Trainium, Microsoft Maia), and every ARM-based server CPU is designed in Synopsys tooling before it touches TSMC for fabrication.

What Synopsys sells

Product line	What it is	Revenue role
Design tools (EDA)	Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime	~50% of revenue, ~70% recurring
Verification	VCS simulator, Verdi debugger, ZeBu emulation	~25% of revenue
IP catalog	~4500 titles — interface IP (PCIe Gen6, USB4, HBM, DDR5), foundation IP, security IP, ARC processor cores	~20% of revenue, fastest-growing segment
ANSYS (closed 2025)	Simulation across multi-physics (thermal, structural, RF)	New segment — expands TAM by ~$5B

Why this is a “pick-and-shovel” play

Every chip designed for AI workloads goes through this funnel:

Architect designs ASIC  →  pays Synopsys + Cadence for EDA tools
       ↓
Designer uses Synopsys IP (PCIe / USB / DDR / HBM)  →  pays IP royalty per chip
       ↓
Verification engineer runs VCS sims  →  pays Synopsys for compute + license
       ↓
Tape out at TSMC  →  Synopsys revenue closes, TSMC revenue starts

Synopsys captures revenue before TSMC ever sees the design, and continues to collect royalty on every chip shipped. Two revenue events per design.

The AI-driven EDA leverage: DSO.ai

The non-obvious 2026 leverage is DSO.ai — Synopsys’ AI-driven design space optimizer. DSO.ai uses reinforcement learning to find better PPA (power, performance, area) targets than human designers, in ~50% less time.

Adoption is real:

NVIDIA disclosed DSO.ai usage on H100/Blackwell design cycles
Samsung Foundry signed multi-year DSO.ai deal for advanced node design
TSMC’s reference flows include DSO.ai as the default for N3/N2

This is “AI designs AI chips” — and Synopsys monetizes the optimization. Each DSO.ai customer pays a premium over baseline EDA — typically 30-50% uplift on the deal size.

The ANSYS acquisition expands TAM

Closed January 2025 for $35B, Synopsys + ANSYS gives the combined entity coverage across:

Chip design (Synopsys core)
Multi-physics simulation (ANSYS — thermal, structural, RF, fluid)
Systems-of-systems modeling (ANSYS + Synopsys digital twin)

Why it matters for AI: thermal modeling at the rack and data-center level is now an EDA problem. Designing a 1.4 MW NVIDIA rack requires thermal simulation that interacts with chip power profiles. ANSYS owns that workflow; Synopsys + ANSYS sells the integrated stack.

Competitive moat

	Synopsys	Cadence	Siemens EDA	Others
EDA share (advanced node)	~35-40%	~30-35%	~15%	~15%
IP catalog size	~4500 titles	~1500 titles	~500	n/a
Foundry reference flows	All major (TSMC, Samsung, Intel)	All major	Some	n/a
AI-driven tools	DSO.ai (lead)	Cerebrus (catching up)	None disclosed	n/a

The Synopsys + Cadence duopoly captures ~70% of all EDA spend. Siemens EDA (formerly Mentor Graphics) is third, well behind on advanced nodes. The duopoly is structural: too much customer-specific tooling, too much foundry validation, too high switching cost to displace.

Risks

EUV / GAA node migration cycle. Customers spend more EDA in node-migration years (N3 → N2 → A16); revenue is bumpy across years.
China export controls. Synopsys has been restricted from selling certain advanced-node EDA into PRC. ~10% revenue exposure.
ANSYS integration. $35B deal — integration risk is real; historical track record of large EDA integrations is mixed.

Practitioner note

For builders depending on chip design:

If you’re building custom silicon (even a small ASIC), Synopsys + Cadence licensing is 80%+ of your design cost. Plan accordingly — EDA license deals are typically 3-year commitments at $1-10M/seat.
DSO.ai shortens design cycles by 30-50%. If your competitor is using it and you’re not, your time-to-silicon is 6-12 months behind on equivalent complexity. For startups, this matters.
Watch the IP catalog adoption rate. Synopsys is increasingly the default for PCIe Gen6 + HBM4 PHY in non-NVIDIA designs. Tracks the same upgrade cycle as Rambus, but with a different customer mix.

The under-considered angle: Synopsys + Cadence are the only two infrastructure-IP names whose revenue depends on chip design starts, not chip shipments. When AI capex pulls forward in advance of TSMC fab buildout (capex announcements precede revenue by 18-24 months), Synopsys is the leading indicator. Watch Synopsys quarterly bookings 6-12 months ahead of the chip shipment cycle.