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Nvidia, AMD, and CoreWeave all backed Tensormesh — KV-cache reuse becomes an inference primitive

Read this because Three rivals — Nvidia, AMD, CoreWeave — co-investing is the tell: KV-cache reuse (don't recompute what you already computed) is being treated as a foundational, neutral inference-stack layer. The economics of the inference era, in one round.

Tensormesh raised $20M from Nvidia, AMD, and CoreWeave and shipped Tensormesh Inference — productized KV-cache reuse claiming up to 10x lower latency/GPU cost.

AMD's 256-core EPYC "Venice" is the first HPC chip to ramp on TSMC 2nm

Read this because Everyone watches the GPU. But AI clusters still need a host CPU to feed them, and AMD just put a 256-core server part on the most advanced node before anyone else. The lever here is efficiency at the power wall — and a quiet Arizona on-shoring story riding alongside it.

AMD is ramping EPYC "Venice" on TSMC 2nm (May 21) — a 256-core/512-thread part, the industry's first HPC product on the node, 70%+ uplift over Turin.

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